Integrated circuits often need to use a reference voltage for signal processing. For example, a bandgap reference voltage has been widely used. However, the reference circuit providing the reference voltage typically does not have enough capability to drive the following circuit (e.g., ADC or DAC). In these situations, a buffer circuit is normally placed between the reference circuit and following circuit to provide the necessary driving capability. For example, a low dropout voltage regulator (LDO) can be used as a reference buffer.
FIG. 1 shows a prior art reference buffer circuit 100. The reference buffer circuit 100 has multiple low-gain wide-band amplifiers to increase an overall transconductance (Gm) and a single Gm stage to drive a following circuit (e.g., the load circuit). The low-gain wide-band amplifiers have a total gain Av=Av1*Av2*Av3 and the total transconductance Gm,t=Av*Gm. The total transconductance Gm,t of the prior art reference buffer circuit 100, however, is sensitive to process, voltage and temperature (PVT) and load current variations.
FIG. 2(a) illustrates a prior art reference buffer circuit 200 that shows details of the reference buffer circuit 100. As shown in FIG. 2(a), a reference voltage Vref is applied to a first input of a first stage amplifier 202, an output voltage Vout of the reference buffer circuit 200 is applied via a feedback loop to a second input of the amplifier 202, the outputs of the second stage amplifier 202 are input to a second stage amplifier 204. The output of the second stage amplifier 202 is coupled to a third stage amplifier. The third stage amplifier includes a resistor Rf, two transistors 206, 208 and two current sources 220 and 222. The output of the third stage amplifier is coupled to a Gm stage that includes a transistor 210 and a current source 224. Av1 of the first stage amplifier and Av2 of the second stage amplifier are determined by the transconductance ratio and device size ratio, and thus, the gains are insensitive to PVT variations. Assuming the transconductance of the transistor 206 is gmn2, then Av3=gmn2*Rf. Further, assuming the transconductance of the transistor 210 is gmpo, then the overall transconductance of the reference buffer circuit 200 is determined by the equation Gm,t=AV1AV2gmn2Rfgmpo∞gmn2Rfgmpo. Thus, the overall transconductance of the prior art reference buffer circuit 200 is sensitive to the PVT variations. In addition, the transconductance of the output stage strongly depends on the load current, and thus, the overall transconductance is also very sensitive to the load current.
FIG. 2(b) illustrates another implementation of the 3rd stage amplifier 238 for a prior art reference buffer circuit. The 3rd stage amplifier 238 has two transistors 242 and 240. Assuming the transconductance of the transistors 240 and 242 are gmp and gmn, respectively, then the output to input ratio is
            v      o              v      i        =            g      mn              g      mp      with the output impedance being
      Z    O    =            1              g        mp              .  This 3rd stage amplifier is a simple active load amplifier and is insensitive to the process variation, but the DC gain is small. In one example application (e.g., an ADC), the required total amplifier gain (Av) is around 70 dB and the simple active load amplifier cannot satisfy the requirement.
The reference buffer often requires a high gain and stability is a concern for the high gain. Therefore, there is a need in the art for providing a reference buffer with a high gain and an overall transconductance that is insensitive to PVT and load current variations.